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NXP Semiconductors /MIMXRT1011 /AIPSTZ1 /OPACR4

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Interpret as OPACR4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TP0)OPAC330 (TP0)OPAC32

OPAC32=TP0, OPAC33=TP0

Description

Off-Platform Peripheral Access Control Registers

Fields

OPAC33

Off-platform Peripheral Access Control 33

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
OPAC32

Off-platform Peripheral Access Control 32

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data